1. Field
Exemplary embodiments of the present invention relate to a delay locked loop (DLL) for use in a semiconductor device.
2. Description of the Related Art
Circuit elements, such as double data rate synchronous DRAM (DDR SDRAM), transmit various signals and data using an internal clock synchronized with an external clock used in an external system. Although a clock inputted to circuit elements is applied in synchronization with an external clock, it may be delayed while passing through elements inside a device, and thus, it may not be outputted to the outside of the device in synchronization with the external clock. To transmit signals and data stably, the internal clock and the external clock should be more exactly synchronized with the external system by reversely compensating the internal clock for a time delay taken to load data onto a bus within the circuit elements, and so on. To this end, a delay locked loop (DLL) may be used in the circuit elements.
FIG. 1 is a block diagram of a conventional DLL.
Referring to FIG. 1, the DLL includes a delay unit 110, a replica delay unit 120, a phase comparing unit 130, a locking unit 140, and a control unit 150.
The delay unit 110 delays an input clock ICLK to generate an output clock OCLK. The replica delay unit 120 has modeled delay values for reflecting a signal delay caused by elements inside a system to which the DLL is applied, and delays the output clock OCLK to generate a feedback clock FBCLK. The phase comparing unit 130 compares a phase of the input clock ICLK with a phase of the feedback clock FBCLK to output a phase comparing result OUT. The control unit 150 increases or decreases a delay value of the delay unit 110 according to the phase comparing result OUT of the phase comparing unit 130. The delay value of the delay unit 110 may be incrementally changed by a unit delay value. When the phase comparing result OUT of the phase comparing unit 130 indicates that the input clock ICLK is synchronized with the feedback clock FBCLK, the locking unit 140 activates a locking signal LOCK that allows the delay unit 110 to maintain a certain delay value at which the input clock ICLK and the feedback clock FBCLK are synchronized.
For reference, the synchronization of the input clock ICLK and the feedback clock FBCLK means that the phases of the two clocks ICLK and FBCLK become equal to each other or the phase difference between the two clocks ICLK and FBCLK become smaller than that caused by the unit delay value.
In general, when the phase of the feedback clock FBCLK leads the phase of the input clock ICLK, the phase comparing result OUT of the phase comparing unit 130 may become a logic low level. In an opposite case, the phase comparing result OUT may become a logic high level. Therefore, when the phase comparing result OUT is a logic low level, the control unit 150 increases the delay value of the delay unit 110 by the unit delay value. Meanwhile, when the phase comparing result OUT is a logic high level, the control unit 150 decreases the delay value of the delay unit 110 by the unit delay value.
Therefore, if the phase comparing result OUT of the phase comparing unit 130 changes from a logic low level to a logic high level because the delay value of the delay unit 110 is increased by the unit delay value, or if the phase comparing result OUT of the phase comparing unit 130 changes from a logic high level to a logic low level because the delay value of the delay unit 110 is decreased by the unit delay value, the phase difference between the input clock ICLK and the feedback clock FBCLK may be smaller than that caused by the unit delay value. That is, in this case, the input clock ICLK and the feedback clock FBCLK are synchronized with each other and therefore the locking unit 140 activates the locking signal LOCK.
However, due to power noise or the like, noise may occur in the phase comparing result OUT. That is, assuming that noise occurs in the phase comparing result OUT, the phase comparing result OUT, which should be maintained at a logic low level, may change to a logic high level. For example, the phase comparing result OUT, which should be maintained as ‘LLLLLL’, may become ‘LLLHLL’ clue to noise. In this case, since the locking unit 140 activates the locking signal LOCK, the phase of the feedback clock FBCLK may be undesirably locked, thus causing a malfunction in the device.